Testing has emerged as a key constraint in the push for more advanced, reliable and cost-effective semiconductor based products. Advances in semiconductor process technology have enabled chip designers to pack high volume production chips with 100 million transistors. Experts predict this will increase to more than 1 billion transistors within the next few years.
Semiconductor process technology is characterized by Moore's Law, which states that the numbers of transistors in a given surface area will double every 18 months. Much of this density increase is driven by smaller and smaller line widths or geometries. Today 90 nm devices are common and 25 nm designs are in development (a nanometer is one billionth of a meter or 1/1200th width of human hair). These advances place a strain on test systems as more transistors and structures must be tested. This exponential growth rate also drives a continual increase in the process, design and manufacturing complexities which, in turn, can increase systemic problems that affect quality, yield and product reliability. All of these factors tend to drive the need for more test time and more comprehensive testing, thus test cost has become a major factor in the overall manufacturing cost of an integrated circuit.
Even with commodity and other products there is an ever-increasing demand by customers to push quality, yield and reliability to new levels. These factors have combined to put major stresses on conventional test capacity and systems. Current solutions to the problem are not cost-effective and rely on either adding expensive capital equipment or relaxing quality standards.
Quality is a known term in the semiconductor industry. One known definition of this term is “a product's nature or features that reflect capacity to satisfy express or implied statements of needs” (Deming, W. Edwards, Out of the Crisis, Cambridge, Mass. Aug. 31, 1993).
Reliability is a known term in the semiconductor industry. One known definition of this term is: “the conditional probability, at a given confidence level, that the equipment will perform its intended functions satisfactorily or without failure, i.e., within specified performance limits, at a given age, for a specified length of time, function period, or mission time, when used in the manner and for the purpose intended while operating under the specified application and operation environments with their associated stress levels” (Kececioglu, Dimitri, Reliability Engineering Handbook, Vol. 1, 2002). Note, incidentally, that these definitions are provided for clarity only and, accordingly, the use of the terms “quality” and/or “reliability” in the context of the invention is by no means bound by these definitions.
Currently, testing is performed by two basic methods. Either, devices are tested one at a time, in singular manner (sequentially); or, several are tested at the same time in “parallel”. Singular tests are more common with complex products such as CPUs while memory devices are most often tested in parallel. Note, however, that these examples are not binding.
As is well known, there are various manufacturing stages including “sort” which aims at testing the semiconductor devices at wafer level and a later final stage which aims at testing the semiconductor devices after having been packaged.
The main goal of the specified stages is to separate out potentially good devices from those that fail testing.
Each of the specified phases is traditionally divided into a few sockets, such as sort1, sort2 etc. Each test socket is applied to the same product (e.g. to all manufactured lots of wafers of the particular product) in a slightly different test flow. For instance, for a given socket, a set of tests is performed at a given temperature, whereas for another socket, the same (or similar) tests are performed at a different temperature. By way of another example, functional tests are applied to the first socket and structural tests are applied to the second socket.
By the same token, the final test phase is divided into distinct stages, such as final1, final2, etc.
As is well known, a semiconductor device is always designed at the single device level. The resulting single prototype is then replicated again and again in the semiconductor fabrication process using lithography or other equipment across the surface of a silicon wafer.
Design for Testability (DFT) is the process in which the device designers create various tests such as functional tests that include the correct patterns and vectors that are used to test the device according to its expected functionality, or creation of parametric tests, etc. A test flow may include functional tests, parametric tests and/or other tests, (whichever the case may be) that are used in the testing process.
Test Program (TP) is composed of test flows that are applied across all the devices on a product in a nearly identical manner. The TP is product specific.
Typically, at a given socket (during sort stage) 100% of all dice are put through the requisite tests and undergo the entire TP (100% TP). In other words, all dice will be subjected to the same test flow, such as continuity, opens, shorts, various functional tests, stuck at scan, at-speed scan, leakage, icc, iddq and/or many more—depending upon various parameters such as the device type.
There are several inherent limitations of the specified testing methodologies, for instance: final IC product reliability can be increased by applying additional tests and stresses, however, since the test program is identically applied over the entire wafer, such a methodology will affect the whole product and thus dramatically increase overall test cost.
Product reliability is a key customer satisfaction issue and affects the reputation of the manufacturer.
Bearing this in mind there follows a list of publications which may be regarded as related art:
U.S. Pat. No. 6,184,048 discloses: A method for assuring quality and reliability of semiconductor integrated circuit devices, fabricated by a series of documented process steps, comprising first, electrically testing the devices outside their specified operating voltage range, yet within the capabilities of the structures produced by the process steps, thereby generating raw electrical test data; second, comparing the test data to values expected from the design of the devices, thereby providing non-electrical characterization of the devices to verify compositional and structural features; and third, correlating the features with the documented process steps to find deviations therefrom, as well as structural defects, thereby identifying outlier devices. After eliminating the outlier devices, the accepted devices do no longer have to undergo the traditional burn-in process.
U.S. Pat. No. 6,618,682 discloses: A method and system are provided that minimize wafer or package level test time without adversely impacting yields in downstream manufacturing processes or degrading outgoing quality levels. The method provides optimization by determining, a priori, the most effective set of tests for a given lot or wafer. The invention implements a method using a processor-based system involving the integration of multiple sources of data that include: historical and real-time, product specific and lot specific, from wafer fabrication data (i.e., process measurements, defect inspections, and parametric testing), product qualification test results, physical failure analysis results and manufacturing functional test results. These various forms of data are used to determine an optimal set of tests to run using a test application sequence, on a given product to optimize test time with minimum risk to yield or product quality.
US 2003/0120457 discloses: A system and method for determining the early life reliability of an electronic component, including classifying the electronic component based on an initial determination of a number of fatal defects, and estimating a probability of latent defects present in the electronic component based on that classification with the aim of optimizing test costs and product quality.
There is a need in the art for a new system and method for augmenting semiconductor integrated circuit quality or reliability through real-time optimal testing. Moreover, there is a need in the art to provide a system and method for applying selectively different test flows to different semiconductor units. The different test flows may apply, for example, to different populations in a wafer or in accordance with another example, to different wafers in a lot. The different populations may be for example different geographies and/or different lithography exposures. The unit may be a whole die or module(s) within a semiconductor device (die). The different test flows may be applied e.g. during sort testing stage and/or during final testing stage.